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Universal Serial Bus 3.0 and 2.0 Specifications

USB 3.0

USB 3.0 specification >: Provides technical details necessary to understand USB 3.0 requirements and design USB 3.0–compatible products.

USB 3.0 internal connector and cable specification >: Describes the internal cable interface for USB 3.0 connections in a desktop, focusing on the electrical and mechanical requirements of the connector, and cable assembly. The detailed daughter card or direct-cable implementation is out of the scope of this documentation.

Intel NUC with USB

PHY interface for the PCI Express* and USB 3.0 architecture specification >

This is a final version of the physical layer (PHY) interface for PCI Express* (PIPE) and USB 3.0 architectures specification that supports PCI Express* and USB 3.0 architectures. The PIPE specification describes a standardized interface between PHY and media access control (MAC) implementations for PCIe* Gen2 and USB 3.0. This document can be used for both discrete PHY parts and for PHYs that are foundry macrocell implementations.

eXtensible Host Controller Interface for USB (xHCI) >

This specification describes the register-level host controller interface for all USB speeds and includes a description of the hardware/software interface between the system software and the host controller hardware.

The specification is intended for hardware component designers, system builders, and device driver (software) developers. The reader is expected to be familiar with the current USB specification revisions.

Adopters can demonstrate compliance of their product(s) with the adopters' agreement.

USB 2.0

PHY interface for the PCI Express* and USB 3.0 architecture specification >

This is a final version of the physical layer (PHY) interface for PCI Express* (PIPE) and USB 3.0 architectures specification that supports PCI Express* and USB 3.0 architectures. The PIPE specification describes a standardized interface between PHY and MAC implementations for PCIe* Gen2 and USB 3.0. This document can be used for both discrete PHY parts and for PHYs that are foundry macrocell implementations.

PHY interface for the PCI Express* and USB 3.0 architecture specification >

This is a final version of the physical layer (PHY) interface for PCI Express* (PIPE) and USB 3.0 architectures specification that supports PCI Express* and USB 3.0 architectures. The PIPE specification describes a standardized interface between PHY and MAC implementations for PCIe* Gen2 and USB 3.0. This document can be used for both discrete PHY parts and for PHYs that are foundry macrocell implementations.

Man using Die'namic Tablet

USB 2.0 specification > (download from the USB-IF web site): Technical details necessary to understand USB 2.0 requirements and to design USB 2.0–compatible products.

On-the-go supplement to the USB 2.0 specification > These specifications address the need for portable devices to communicate with each other and with USB peripherals when a PC is not available.

Enhanced host controller interface (EHCI) compliance testing program >

The EHCI compliance testing program measures an EHCI controller implementation for conformance to the EHCI specification and evaluates the functionality of the EHCI controller function of a USB 2.0 host controller. It does not evaluate the functionality of the USB companion controllers.

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xHCI adopters' agreement

Adopters' agreement for xHCI specification for USB >

Adopters can demonstrate compliance of their product(s) with the specification through the xHCI compliance testing program provided by Intel.

For details on the program contact us.

Note: In case of conflicts between the xHCI and the USB specifications, the USB specifications take precedence and must be followed.

Enhanced host controller interface (EHCI) specification

Information includes licensing, revisions, addendums, and technical questions.

EHCI specification >