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PHY Interface for PCI Express

The PCI Express*, SATA and USB SuperSpeed PHY interface specification has definitions of all functional blocks and signals. This revision includes support for PCI Express implementations conforming to the PCI Express Base specification, revision 3.0, SATA implementations conforming to the SATA specification, revision 3.0, and USB implementations conforming to the Universal Serial Bus (USB) specification, revision 3.0.

The PHY Interface for the PCI Express, SATA, and USB SuperSpeed Architectures (PIPE) is intended to enable the development of functionally equivalent PCI Express, SATA and USB SuperSpeed PHY's. Such PHY's can be delivered as discrete IC's or as macrocells for inclusion in ASIC designs. The specification defines a set of PHY functions which must be incorporated in a PIPE compliant PHY, and it defines a standard interface between such a PHY and a Media Access Layer (MAC) & Link Layer ASIC. It is not the intent of this specification to define the internal architecture or design of a compliant PHY chip or macrocell. The PIPE specification is defined to allow various approaches to be used. Where possible, the PIPE specification references the PCI Express base specification, SATA 3.0 specification or USB 3.0 specification rather than repeating its content. In case of conflicts, the PCI-Express base specification, SATA 3.0 specification, and USB 3.0 specification shall supersede the PIPE spec.

Read the full PHY Interface for the PCI Express, SATA and USB 3.0 Architectures specification update.

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