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Xilinx Spartan*-6 PCIe* I/O Control: Guide

Xilinx Spartan-6* PCIe* I/O Control: Guide

Overview
This reference design uses a simple hardware design that interfaces the LEDs, DIP switches, and push buttons to the PCI Express* core through registers in the FPGA. A simple driver and software application are provided that allow the user to control this board I/O through a graphical user interface in Windows* XP.

Objectives
The objectives of this reference design are:
• Show a simple, register-mapped I/O adaptation based on the Xilinx programmed I/O design.
• Use an example driver to communicate over PCI Express with Software.
• Use a graphical user interface to control the driver, which in turn controls the PCI Express Endpoint hardware.

Read the full Xilinx Spartan-*6 PCIe* I/O Control Guide.

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