Product Features Datasheet ■ IEEE 802.3ab compliant —Robust operation over the installed base of Category-5 (Cat-5) twisted pair cabling ■ Robust end to end connections over various cable lengths ■ Full duplex at 10, 100, or 1000 Mbps and half duplex at 10 or 100 Mbps. ■ IEEE 802.3ab Auto-negotiation with Next Page support —Automatic link configuration including speed, duplex, and flow control ■ 10/100 downshift —Automatic link speed adjustment with poor quality cable ■ Automatic MDI crossover —Helps to correct for infrastructure issues ■ Advanced Cable Diagnostics —Improved end-user troubleshooting ■ Footprint compatible with 82562V devices for a single-board dual design (Gigabit and 10/100) ■ LCI interface for a very low power 10/100 link ■ Gigabit LAN Connect Interface —Low pin count, high speed interface with special low power idle modes —Allows PHY placement proximity to I/O back panel. ■ 3 LED outputs —Link and Activity indications (10, 100, and 1000 Mbps) ■ Clock supplied to MAC —Cost optimized design ■ Full chip power down —Support for lowest power state ■ 81-pin, 1.0 mm pitch, 10 mm x 10 mm FCMMAP (BGA) Package —Smaller footprint and lower power dissipation compared to multi-chip MAC and PHY solutions. Footprint ® compatible with the Intel 82562V Platform LAN Connect device ■ Integrated voltage regulator and power supply control, which can be powered from a single 3.3V DC rail ■ Operating temperatures: 0° C to 70° C and 0° C to 55° C (with internal regulator) – heat sink or forced airflow not required —Simple Thermal Design ■ Power Consumption less than 1.16 Watts (silicon power) 317436-003 Revision 2.4 Revision History Date December 2007 August 2007 May 2007 August 2006 June 2006 March 2006 Revision 2.4 2.3 2.2 2.1 2.0 1.5 Comments • Removed 802.3 SerDes reference in section 1.0. • Updated Section 1.2. Added reference document “Implementing the Intel® Auto Connect Battery Saver (ACBS) With the Intel® 82566”. • Added ICH9 information. • Added new power consumption table for the 82566 DC/DM. • Change ballout row “I” to “J”. Changed all “I” pinout designations to “J”. • Updated crystal specifications. • Replaced Figure 4. • Removed Vcase parameter from Table 9. • Removed section 3.4 “Thermal Diode (TD)”. This information can now be found in the 82566 Gigabit Platform LAN Connect Thermal Design Considerations Application Note. • Revised section 4.2 title. • Revised Table 10 (removed operating temperature range parameter and related notes). • Changed all “J” pinout designations to “I” to match Figure 10 “Visual Pin Assignments”. Initial public release. • Added note to Table 16. Initial Intel Confidential release. Legal Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING Read the full 82566 Gigabit Platform LAN Connect Networking Silicon.